Tablegen: Instructions that take immediates or registers as operands

Hi,

I'm working on an LLVM backend for GPUs. One thing that is a little
different about some GPUs is that instructions can take registers or
32-bit floating point immediates as arguments. I was wondering if there
is a way to model this using tablegen, without having to define an
instruction for each possible combination of registers and immediates
(e.g. For ADD it would require four definitions: ADD_imm_imm,
ADD_reg_reg, ADD_imm_reg, ADD_reg_imm).

I have tried a few different ways to make this work in tablegen, but I
have been unsuccessful so far. Here is an example of something I have
tried. It fails to compile with tablegen, but I hope it can help
demonstrate what I am trying to do:

def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>;

def F32Op : Operand <f32> {
  let MIOperandInfo = (ops GPR, f32imm);
}

def ADD : InstAMD <
          (outs GPR:$dst),
          (ins F32Op:$src0, F32Op:$src1),
          "ADD $dst, $src0, $src1"),
          [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))]
  >;

Is what I am trying to do possible with tablegen, and if so what is the
best way for me to do it?

Thanks,
Tom Stellard

Tom,
There is no way to do this that I know of. Maybe David Greene or someone who hacks on Tablegen a lot would know.

Micah

Tom,
There is no way to do this that I know of. Maybe David Greene or someone who hacks on Tablegen a lot would know.

This particular problem is not so bad with the use of multiclass and mdef. It at least lets you factor out the redundancy across different instructions.

"Villmow, Micah" <Micah.Villmow@amd.com> writes:

Tom,

There is no way to do this that I know of. Maybe David Greene or
someone who hacks on Tablegen a lot would know.

There's no way currently without major TableGen hacking.

                        -Dave