(tablegen) Machine instruction without result

Hello,

I am working on the backend for an architecture which has a compare instruction that affects only an internal condition code register (basically a sub without destination register).
I get the following assert in the scheduling phase:

  llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < NumValues && "Illegal result number!"' failed.

It turns out that ResNo and NumValues are both 1, which makes me think somehow the no-result aspect has not been properly modelized. Therefore, I suspect my tablegen description of this instruction to be erroneous, so I paste it below with comments what I think I am doing:

//define an instruction profile with zero results,
//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
  SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;

//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;

//define the instruction
def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
                          "cmp $src1 $src2;",
                          [(MYcmpicc IntRegs:$src1, IntRegs:$src2)]>;

Thanks for having a look on this.
If the problem lies not in my .td files, where else do you think I could dig for the cause of this error?

Thank you,
Christian

Hello,

I am working on the backend for an architecture which has a compare instruction that affects only an internal condition code register (basically a sub without destination register).

You want to model the condition codes as a pseudo-register rather than using OutFlag. See the X86 back end.

Hello,

I am working on the backend for an architecture which has a compare
instruction that affects only an internal condition code register
(basically a sub without destination register).

You want to model the condition codes as a pseudo-register rather than
using OutFlag. See the X86 back end.

To clarify. x86 is modeling the condition code register EFLAGS and it's being treated as a physical register. This allows it to express a dependency between a cmp and a branch instruction.

Evan