Tablegen pattern matching question

Hi all,

I want to match addition with 16bit integers. So I define a pattern fragment as follows:

def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;

Now I am confused between
(add R32:$dst, simm16:$im) and
(add R32:$dst, (i32 simm16:$im)).

Do both of them match the same pattern? Are they equivalent? If not what is the difference?
I am also confused as to how ValueTypes relate to SDNodes as I think we are able to use both of them as nodes.

What are you trying to add, I see you have a result $dst of register class R32 and an imm src operand, what is being added? This looks more like a move to me. And in the second example you are trying to force simm16:$I’m to i32?

-Ryan

Patterns are able to infer types based on constraints specified on the SDNode class (in this case the “add” node. The “add” node is defined as requiring both inputs to be the same type. I presume R32 register class is defined as only supporting i32 types. So the type of the immediate operand is inferred to be i32 and you don’t need to specify it. You should get a build failure if you write

(add R32:$dst, (i16 simm16:$im)).

This will be a type constradiction since the operands of the add don’t have the same type.

Thanks for the information. Just a few more questions.

Does (i32 simm16:$im) mean casting $im to i32?
Do dags like (ValueType otherDag) correspond to separate SDNodes with
'otherDag' node as input? or do they just change the type annotation of the
'otherDag' node.

So I should have added the complete pattern. I'm trying to achieve rd = rd
+ imm. While reading the sparc backend code I came across the above casting
pattern and hence the confusion.
let Constraints = "$rd = $dst" in {
.. [(set R32:$rd, (add R32:$dst, simm16:$im) )]
}