tablegen puzzle

Is there a way to define an instruction so that certain registers are clobbered after
the instruction but not by saying they are Defs?

There are some subtle differences where if you use Defs for special registers that are not normally
assigned to the register allocator.

The issue I'm having is with AC0 and HI/LO for Mips when doing fast-isel.

AC0 has HI/LO as subregisters.

After a normal MUL, HI/LO are undefined; in other words they are clobbered but the tablegen
says they are are defined (otherwise instruction scheduling could mess things up).

But because of the fact that AC0, HI/LO are "disabled", when HI/LO is set as being dirty,
the value is never cleared and then AC0 cannot be allocated because the register allocator
thinks that HI/LO have valid data that is in use.