TableGen question - how to split a 64bit operation to two 32bit

Hi all,
I’m working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate.
Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM source code? (I was looking for it but couldn’t find it)

Thanks,
Artur

Hello, Artur

I'm working on my own backend for a custom CPU. I have defined paired
registers for 64bit operations, however to set a 64bit paired register with
64bit immediate I have to set each register in that pair separately with the
higher and the lower 32bits of the immediate.
Could anyone give me an advice how to describe it in *InstructionInfo.td or
point me to something similar in the LLVM source code? (I was looking for it
but couldn't find it)

There are several possible ways of doing so. One is to work at
asmprinter level. Also, many processors have separate instructions to
set e.g. low and high 16 bits of the whole 32 bit register. You might
want to see, how the stuff is done there (you'll need a custom operand
matching function + transform). See, e.g. arm, systemz, powerpc
backends.

Hi Artur,

The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a 32-bit constant by a two-instruction sequence to load the low and high half-words. It's not pretty, but it works. The pattern is at the bottom of the file.

Regards,
-Jim

Hi Jim,

Hi Artur,

The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a 32-bit constant by a two-instruction sequence to load the low and high half-words. It’s not pretty, but it works. The pattern is at the bottom of the file.

Regards,
-Jim

Wow, somehow I’ve missed that when I was looking in the source. Thanks a lot.

Artur