TableGen questions.

Hello all,

I have two Tablegen questions in the context of an unconventional architecture. The pertinent details: the architecture has multiple register files that are selected via a bit in the instruction. One of the register files is a traditional one. The other is unconventional in that all source and dest registers are both read from and written to by the instructions. So

add special0, special1, special2

would require both the ins and outs dags in the instruction info to have all three registers, if I understand the scheduler correctly.

My questions:

  1. Is my assumption that both ins and outs dags must have all three special registers correct?
  2. Is there a way to template ins and outs and mix that with multiclass, or do I need to elaborate all options? I can’t find a similar example where ins and outs are conditionally populated for an instruction.

Right now I’m using 4.0.1. I used to have the if(eq()) embedded in the templates, but that doesn’t generate. I’m currently trying to create a class containing the ins and outs dags, using if(eq()) extensively, so that the multiclass template for the instructions is a single line. Code follows (probably not correct due to name mangling).

class IO_MultSrc<bits<2> op0Type, RegisterClass Src0RC> {
dag insDefault = !if(!eq(op0Type, 0b01),

(ins SpecialReg:$dst, Src0RC:$a),
(ins Src0RC:$a));


multiclass MultSrc1Spec<bits<5> subOpcode, bits<2> op0t, string opcodeStr, RegisterClass RegType> {
def _allspecial:
MultSrcOneDestInst<subOpcode, op0t, 0b00,
IO_MultSrc<op0t, SpecialReg>.outsDefault,
IO_MultSrc<op0t, SpecialReg>.insDefault>;


multiclass TwoSrcOneDestSpec<bits<5> subOpcode, string opcodeStr> {

defm _dds: MultSrc1Spec<subOpcode, 0b10, opcodeStr, SpecialReg>;

defm _rr: MultSrc1Spec<subOpcode, 0b11, opcodeStr, GPReg>;

defm ADD : TwoSrcOneDestSpec<0b10000, “add”>;

I currently get the error “Undefined reference:‘ADDanonymous_545’” when I try to generate.

Any advice would be greatly appreciated, even if that advice is “don’t try to conditionally set ins and outs.”


I suspect that the use of IO_MultSrc here is the culprit. TableGen has some limitations here, when it comes to instantiating classes "inline", like in the example above. Try instantiating the IO_MultSrc for these arguments separately and passing the ins/outs as parameters.