I’m facing a crash in TableGen (as of 7.0) when generating register info for our out-of-tree target.
llvm-tblgen: llvm/utils/TableGen/CodeGenRegisters.cpp:128: void llvm::CodeGenSubRegIndex::setConcatenationOf(llvm::ArrayRefllvm::CodeGenSubRegIndex*): Assertion `std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) && “parts consistent”’ failed.
It should reproduce, even on tip, with the example RegisterInfo file I’ve pasted below. Run with: llvm-tblgen -gen-register-info -I /path/to/llvm/include TestRegInfo.td
It’s something to do with SUPER1 and SUPER2 using the same index (SubRegLo32) to index subregisters which themselves contain differently-composed subregisters from one another: SuperQ has four quarters but I1 has two halves.
My question is: is this a documented restriction in TableGen or a bug? If it’s a design choice, should it emit a more appropriate error rather than asserting?