I was trying to create a model for a subtarget of the ARM processors. Though, I’ve been experiencing some issues. In particular, it seems like TableGen does not consider SchedWriteRes defined in the subtarget but only the ones defined in the ARM target.
For example, I defined a subtarget SchedWriteRes mapped onto its right functional units for ANDri instructions but the instruction does not follow what is defined for that SchedWriteRes, but the one defined for the WriteALUri in the ARM target.
It may be possible that TableGen does not consider SchedWriteRes defined in sub targets?