[TableGen] What to do if there are overlapping instruction patterns?

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers.

The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U (Espresso)

It's been going pretty well so far, however the biggest hurdle I have encountered was that the testsuite is failing because the instruction space for Paired Singles has been reused for ISA 3.1 and VMX.

Is there a way to disembiguate them further? You can see my current patch at https://reviews.llvm.org/D85137 and it already prevents you from enabling Altivec and Paired Singles at the same time.

I should have added the decoding conflicts output generated by the build step of PPCGenDisassemblerTables.inc in my previous email. Most worrisome is is the psq_st entry as that conflicts with over a hundred entries, however this is the immediate-offset store instruction for paired singles which makes it quite important

decoding-conflicts.txt (14.4 KB)

Hi, Charlotte,

You can set a different decoding namespace for the new instructions. We have this for SPE instructions, and this is what we did for QPX instructions when those were supported.

In TableGen, you surround the instructions with something like:

let DecoderNamespace = "PairedSingles" in {

and then in Disassembler/PPCDisassembler.cpp, you'll have something like:

if (STI.getFeatureBits()[PPC::FeaturePairedSingles]) {
DecodeStatus result =
decodeInstruction(DecoderTablePairedSingles32, MI, Inst, Address, this, STI);
if (result != MCDisassembler::Fail)
return result;
} else if (STI.getFeatureBits()[PPC::FeatureSPE]) {

-Hal

Hi Hal,

Didn't know about that, it seems to work. thank you for your quick response.