TargetParser: auto-generation of RISCV CPU definitions

Here is my proposal for the same style of split, but for all targets, not just RISC-V: ⚙ D137838 [RFC][Support] Move TargetParsers to new component

This takes all of the Target Parsers, and puts them in the same, new component. The difficult parts are:

  • llvm/ADT/Triple.h is moved into this component because it depends on the Arm target parsers.
  • llvm/Support/Host.h is moved into this component because it depends on the x86 target parser.

This would then allow more targets than just RISC-V to use tablegen in their target parsers.

This has several dependent patches:

There are likely further cleanups I might do in future, given e.g. the x86 target parser has a copy of FeatureBitset from llvm/MC/SubtargetFeature.h. I think it might be better to have this data structure just live in llvm/TargetParser, maybe along with some of the other feature handling utility classes.

One thing I wasn’t sure about was whether we should be moving the target-specific Build Attribute handling code in Support into this component too. I think we can do that later if we choose to.

Comments welcome.

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