testing of insert element instruction

I’m trying to test an insert element into a vector instruction (vsetitem ). And I’ve written a simple test for it. Basically I just want to see if it works. However When I run it through llc I get a following error:

LLVM ERROR: Cannot select: 0x2ac3180: v4i32 = vector_shuffle 0x2ac2f70, 0x2ac3078<0,4,u,u> [ORD=3] [ID=10]
0x2ac2f70: v4i32 = scalar_to_vector 0x2ac38b8 [ORD=3] [ID=8]
0x2ac38b8: i32,ch = CopyFromReg 0x2a9c8b0, 0x2ac37b0 [ORD=1] [ID=5]
0x2ac37b0: i32 = Register %vreg4 [ID=1]
0x2ac3078: v4i32 = scalar_to_vector 0x2ac3ac8 [ORD=3] [ID=9]
0x2ac3ac8: i32,ch = CopyFromReg 0x2a9c8b0, 0x2ac39c0 [ORD=1] [ID=6]
0x2ac39c0: i32 = Register %vreg5 [ID=2]
In function: foo

I’m kind of confused why it needs a shuffle instruction? Any way to test my instruction without using a shuffle?

Any help is appreciated. The test case is provided below.

; ModuleID = ‘build-vector.c’
target datalayout = “E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32”
target triple = “esencia”

; Function Attrs: nounwind
define void @foo(i32 %b1, i32 %b2, i32* nocapture %res) #0 {
%0 = insertelement <4 x i32> undef, i32 %b1, i32 0
%1 = insertelement <4 x i32> %0, i32 %b2, i32 1
%2 = bitcast i32* %res to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4, !tbaa !1
ret void