Took chisel-circt 0.6.0 and LLVM 1.15.0 for a spin

Easier than in May when I tried last. There are now binaries and chisel-circt is a bit smoother.

The showstopper for me is still the lack of BoringUtils annotations firtool though:

circuit Foo :
<stdin>:1:1: warning: Unhandled annotation: {class = "firrtl.passes.wiring.SinkAnnotation", pin = "bore_120", target = "[2]"}

Any ETA on when this annotation will be supported?

I tried LLVM 1.20.0 and it is not in that version.

What is your use case for BoringUtils? It currently hasn’t been prioritized.

I’m using it to instrument my design on an FPGA.

It is a type-safe, unit-testable and easier to maintain and set up alternative to e.g. ChipScope from Xilinx or SignalTap from Altera.

Unlike SignalTap/ChipScope, when I used those, this instrumentation can also change signals and inject data/tests into the design.

Automated non-functional regression tests of the design in the FPGA on pull requests, e.g. performance counters to check that the performance does not drop.