tricky constraints in backend

Hi,

I am working on custom LLVM 3.7 backend, already having GCC backend.
In GCC backend there are perfectly legal address constraints like
"A32", which are widely used in inline assembler.

I am trying to support those in LLVM, but there is a problem in
llvm::InlineAsm::ConstraintInfo::Parse function.

it tries to understand A32 as two separate constraints: one-letter "A"
and numeric "32", latter, of course, fails (numeric 32 constraint
means "32-nd parameter", and there are no 32 parameters).

It is called very early, from llvm::InlineAsm::InlineAsm ctor, where
assert fails for this reason, so even llvm IR is not emitted.

Is there a way to support multi-letter target-specific constraints
with trailing digits?

Hi,

Internally, multi-character constraint codes need to begin with '^' but there's currently FIXME that will prevent your case from working. The code currently assumes that there's a maximum of two characters after the '^', so '^A3' would work but '^A32' would by the constraints 'A3' and '2'. You should be able to get your case working by fixing that FIXME and updating the documentation (http://llvm.org/docs/LangRef.html#constraint-codes) to match.

By the way, I noticed a mistake in that documentation while I was writing this. The documentation says 'a ā€œ^ā€ character followed by two letters (e.g. ā€œ^wcā€)' but the implementation doesn't restrict it to just letters.