TTA-based Co-Design Environment (TCE) v1.21 Released

TTA-based Co-Design Environment (TCE) is an open application-specific
instruction-set processor (ASIP) toolset for design and programming of
customized co-processors (compiler-programmable accelerators). It is
based on the energy efficient Transport Triggered Architecture (TTA)
processor template.

The toolset provides a complete retargetable co-design flow from high-
level language programs down to FPGA/ASIC synthesizable processor RTL
(VHDL and Verilog generation supported) and parallel program binaries.

The size and quantity of register files, function units, supported
operations, and the interconnection network can be freely customized to
create new co-processors ranging from small single-application specific
cores with special operations to static multi-issue domain-specific processors.

Notable Changes