use of ARM GPRPair register class

Hi,

I am experimenting with creating instructions that write into virtual registers that use the ARM GPRPair register class in Pre-RA phase.

During register allocation, I hit an assertion because the code is not in SSA form:

lib/CodeGen/MachineRegisterInfo.cpp:271: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || llvm::next(I) == def_end()) && “getVRegDef assumes a single definition or no definition”’ failed.

The code in lib\CodeGen\MachineRegisterInfo.cpp has information about the virtual register’s sub-register been written, but that info is not propagated to getVRegDef.

Is it possible/ is there any plan to update the code analysis to distinguish virtual register’s sub-registers definitions? So that GPRPair sub-registers can be used by instructions that do not return 64 bit value?

Example:

This is a simple example of machine instructions I caused to be generated. I forced the LDRi12 instructions to use a GPRPair sub-register.

The copy into %vreg4 asserts because of the two definitions of vreg9, coming from vreg9:gsub_0 and vreg9:gsub_1.

%vreg1 = COPY %R1; GPR:%vreg1

%vreg2 = MOVi32imm ga:a; GPR:%vreg2

%vreg3 = ADDrsi %vreg2, %vreg1, 18, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg3,%vreg2,%vreg1

%vreg9:gsub_0<def,read-undef> = LDRi12 %vreg3, 112, pred:14, pred:%noreg; mem:LD4%arrayidx83 GPRPair:%vreg9 :%vreg3

%vreg9:gsub_1<def,read-undef> = LDRi12 %vreg3, 116, pred:14, pred:%noreg; mem:LD4%arrayidx86 GPRPair:%vreg9 :%vreg3

%vreg4 = COPY %vreg9:gsub_0; GPR:%vreg4 GPRPair:%vreg9

%vreg5 = COPY %vreg9:gsub_1; GPR:%vreg5 GPRPair:%vreg9

%vreg6 = LDRi12 %vreg3, 120, pred:14, pred:%noreg; mem:LD4%arrayidx89 GPR:%vreg6,%vreg3

%vreg7 = ADDrr %vreg4, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg7,%vreg4,%vreg5

%vreg8 = ADDrr %vreg7, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg8,%vreg7,%vreg6

%R0 = COPY %vreg8; GPR:%vreg8

BX_RET pred:14, pred:%noreg, %R0

Thanks,
Ana.

No, the code before register allocation must be in SSA form. That means every virtual register has one def, whether it is a sub-register def or not. The machine code verifier should tell you this loudly.

You should be able to use REG_SEQUENCE and/or INSERT_SUBREG to do what you want while preserving SSA form.

/jakob