Use of llvm.prefetch intrinsic for basicblock prefetching

Hi,

I am new to LLVM and using it for my project where I want to perform software prefetching of code blocks.

I am not able to use the llvm.prefetch instruction to fetch a block of code in instruction cache. The LangRef manual mentions that giving last argument as ‘0’ performs prefetch on instruction cache.

However, I get the following error when I do that.

LLVM ERROR: Cannot select: 0x2a39348: ch = Prefetch 0x2a39030, 0x2a39138, 0x2a38c10, 0x2a39240, 0x2a38c10<LD1[%x1]> [ORD=9] [ID=15]
0x2a39138: i64 = FrameIndex<1> [ID=4]
0x2a38c10: i32 = Constant<0> [ID=1]
0x2a39240: i32 = Constant<1> [ID=5]
0x2a38c10: i32 = Constant<0> [ID=1]
In function: main

What does this error mean?

Can anyone please tell me if I can inform the processor to prefetch code to instruction cache?

Thanks in advance.

Usha

From: "usha shau" <ushashau1@gmail.com>
To: llvmdev@cs.uiuc.edu
Sent: Monday, September 22, 2014 7:01:20 AM
Subject: [LLVMdev] Use of llvm.prefetch intrinsic for basicblock prefetching

Hi,

I am new to LLVM and using it for my project where I want to perform
software prefetching of code blocks.
I am not able to use the llvm.prefetch instruction to fetch a block
of code in instruction cache. The LangRef manual mentions that
giving last argument as '0' performs prefetch on instruction cache.
However, I get the following error when I do that.

LLVM ERROR: Cannot select: 0x2a39348: ch = Prefetch 0x2a39030,
0x2a39138, 0x2a38c10, 0x2a39240, 0x2a38c10<LD1[%x1]> [ORD=9] [ID=15]
0x2a39138: i64 = FrameIndex<1> [ID=4]
0x2a38c10: i32 = Constant<0> [ID=1]
0x2a39240: i32 = Constant<1> [ID=5]
0x2a38c10: i32 = Constant<0> [ID=1]
In function: main

What does this error mean?
Can anyone please tell me if I can inform the processor to prefetch
code to instruction cache?

It means that the target backend does not implement that prefetch variant and that it does not provide the appropriate fall-back behavior. What architecture are you targeting?

Generally speaking, please file a bug report.

-Hal

Hi,

Thanks,

I am targetting x86 architecture.

-Usha

From: "usha shau" <ushashau1@gmail.com>
To: "Hal Finkel" <hfinkel@anl.gov>
Cc: llvmdev@cs.uiuc.edu
Sent: Monday, September 22, 2014 10:09:31 PM
Subject: Re: [LLVMdev] Use of llvm.prefetch intrinsic for basicblock prefetching

Hi,

Thanks,
I am targetting x86 architecture.

Interesting; looks like something needs to be fixed. Please file a bug using http://llvm.org/bugs/ (select "libraries" as the product and "Backend: X86" as the component).

-Hal

I have a filed a bug regarding this.

To achieve my goal of block prefetching using llvm, can I modify the llvm.prefetch instrinsic implementation to handle the icache prefetch variant for X86 target? Is this possible?

Or will I have to add a new instruction to llvm. I am planning to modify a CPU simulator that will support this instruction or the icache intrinsic for X86 target.

I just need some starting point as to where to make the modifications in LLVM.

Thanks,

Usha