Uses, Defs, ins, outs, params in tablegen instruction definition

Hi, I'm working on a Z80 backend and I'm trying to get the instruction definitions right, but couldn't find a clearly detailed explanation about the parameters, specifically "Uses" and "Defs".
I looked especially at the X86 tables, but don't really get it - e.g. for ADD and MUL, there are different approaches and parameter-setups, where I would expect almost equal instruction definitions.

About "Uses" and "Defs", include\llvm\Target\Target.td says:

   Uses - Default to using no non-operand registers
   Defs - Default to modifying no non-operand registers

As an example, let me take X86's "ADD" and "ADC" commands and assume that they have only the "AL" form, and taking a look only at adding other registers. To make it easier, let's for now not consider multiclass and pattern-setup.

ADD AL,r/m/i -> DST = DST + SRC, overflow result in Carry
ADC AL,r/m/i -> DST = DST + SRC + Carry, overflow result in Carry

DST is (always, only): AL
SRC is reg / mem / imm

Now for the definition:
Assuming the following register classes:
- "AR" has register AL only
- "EFLAGS" has the status / flags register only
- "GR" has all other registers

The instruction format is:

let Uses = [...], Defs = [...] in {
ITy<...(outs ...),(ins ...), ...
[(set ...dst..., EFLAGS,
    (...SDNode<...,IsCommutable>, ...param1..., ...param2...))]>;

For "ADD AL,r" what would be the Uses, Defs, outs, ins, param1, param2? I would expect the following:
Uses = [AL]
Defs = [AL, EFLAGS]
(outs AR:$dst)
(ins GR:$src)
set AL, EFLAGS, ...
param1: AL
param2: GR:$src

For "ADC AL,r", I would expect the only difference to be
Uses = [AR, EFLAGS]

But, as to my understanding and looking at the X86 definitions, this is not correct, or too much.

So here are my questions:
- What (registers and / or register classes) is required in each, Uses, Defs, ins, outs, param1, param2?
- can I use the register definition instead of the register class if it contains only one register?
- Does the order of param1 and param2 matter in the case of a commutable operation?
- When adding AL, AL, I could also do a left-shift-into-carry. If the shift operation would be cheaper, how could this be represented?

Thanks,
Michael

Hi Michael,

Hi, I'm working on a Z80 backend and I'm trying to get the instruction definitions right, but couldn't find a clearly detailed explanation about the parameters, specifically "Uses" and "Defs".
I looked especially at the X86 tables, but don't really get it - e.g. for ADD and MUL, there are different approaches and parameter-setups, where I would expect almost equal instruction definitions.

About "Uses" and "Defs", include\llvm\Target\Target.td says:

Uses - Default to using no non-operand registers
Defs - Default to modifying no non-operand registers

As an example, let me take X86's "ADD" and "ADC" commands and assume that they have only the "AL" form, and taking a look only at adding other registers. To make it easier, let's for now not consider multiclass and pattern-setup.

ADD AL,r/m/i -> DST = DST + SRC, overflow result in Carry
ADC AL,r/m/i -> DST = DST + SRC + Carry, overflow result in Carry

DST is (always, only): AL
SRC is reg / mem / imm

Now for the definition:
Assuming the following register classes:
- "AR" has register AL only
- "EFLAGS" has the status / flags register only
- "GR" has all other registers

The instruction format is:

let Uses = [...], Defs = [...] in {
ITy<...(outs ...),(ins ...), ...
[(set ...dst..., EFLAGS,
(...SDNode<...,IsCommutable>, ...param1..., ...param2...))]>;

For "ADD AL,r" what would be the Uses, Defs, outs, ins, param1, param2? I would expect the following:
Uses = [AL]
Defs = [AL, EFLAGS]
(outs AR:$dst)
(ins GR:$src)
set AL, EFLAGS, ...
param1: AL
param2: GR:$src

Uses and Defs is for *implicit* uses and defs, and it takes registers (not register classes), so you'd only have EFLAGS (as a register) in there.

Outs and Ins always need to be listed fully, so you'd have

(outs AR:$dst)
(ins AR:$src1, GR:$src2)

and then set Constraints to "$dst = $src1", to encode the fact that you're really talking about a two-operand instruction here.

The AR / GR do have to be register calsses as far as I'm aware.

Cheers,
Nicolai