I’ve got an instruction that has the following pattern (R32C is the 32-bit register class):
(set R32C:$rT, (or (and R32C:$rA, R32C:$rC),
(and R32C:$rB, (not R32C:$rC))))
tblgen generates the following variants (I’ve dropped the R32C for brevity):
(or (and $rA, $rC), (and $rB, (not $rC))) # original
(or (and $rA, $rC), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rA, $rC))
(or (and (not $rC), $rB), (and $rA, $rC))
I would have expected four additional patterns, each with the (and $rC, $rA) variant in it. But I only get the above four.
Is this a bug or a feature? 
-scooter
This is a feature. They would match the same pattern, so it would just be generating dead code. For the same reason, if you write something like:
(set $rd, (and $rs, 123))
you will only get matching code for that pattern, and not for:
(set $rd, (and 123, $rs))
which is always canonicalized to the former.
-Chris
I’m not sure how much of a feature that is – evidently, in my particular case, enumerating all eight variants ends up generating the desired code. Leaving llvm to its own devices doesn’t generate the desired code. I would have expected that the “(and $rA, $rC)” to match “(and $rC, $rA)”, were they inverted, but it doesn’t get generated in my test code.
Generated patterns:
(or (and $rA, $rC), (and $rB, (not $rC))) # original
(or (and $rA, $rC), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rA, $rC))
(or (and (not $rC), $rB), (and $rA, $rC))
Missing patterns:
(or (and $rC, $rA), (and $rB, (not $rC)))
(or (and $rC, $rA), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rC, $rA))
(or (and (not $rC), $rB), (and $rC, $rA))
-scooter
I'm not sure how much of a feature that is -- evidently, in my particular case, enumerating all eight variants ends up generating the desired code. Leaving llvm to its own devices doesn't generate the desired code. I would have expected that the "(and $rA, $rC)" to match "(and $rC, $rA)", were they inverted, but it doesn't get generated in my test code.
You haven't given me the full description for the instruction. Are $rA/$rB/$rC all the same register class? Please include the full instruction description and do the equivalent of:
$ cd lib/Target/X86
$ tblgen X86.td -I ../ -I ~/llvm/include/
to get the expanded definition of your instruction. With that, maybe I'll have a more precise answer for you
Thanks,
-Chris
Generated patterns:
(or (and $rA, $rC), (and $rB, (not $rC))) # original
(or (and $rA, $rC), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rA, $rC))
(or (and (not $rC), $rB), (and $rA, $rC))
Missing patterns:
(or (and $rC, $rA), (and $rB, (not $rC)))
(or (and $rC, $rA), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rC, $rA))
(or (and (not $rC), $rB), (and $rC, $rA))
-scooter
-Chris