VirtRegMap Error

I just updated from upstream llvm as of about last Thursday and I'm
getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps.
It seems that the particular instruction being removed happens
to reference an object at stack slot 4. The first spilled register is
assigned stack slot 6 so LowSpillSlot == 6. Then, when we try to
erase from SpillSlotToUsesMap, we index with a negative number.

The instruction being removed is generated by instruction selection,
so it is part of the original program:

%reg1309<def> = FsMOVLPDrm <fi#4>, 1, %reg0, 0, Mem:LD(8,8) [ZETA + 0]

Since we're hooking up llvm to custom code, I want to check assumptions.
Is there anything in llvm-gcc or the other llvm tools that could generate a
stack slot reference like this before register allocation? Basically, I'm
trying to see if only our code could ever do this. Otherwise, we have a bug
in llvm. Is everything on the stack assumed to be mem2reg'd and so this
never happens with llvm tools?

Thanks.

                                                -Dave

I just updated from upstream llvm as of about last Thursday and I'm
getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps.
It seems that the particular instruction being removed happens
to reference an object at stack slot 4. The first spilled register is
assigned stack slot 6 so LowSpillSlot == 6. Then, when we try to
erase from SpillSlotToUsesMap, we index with a negative number.

The instruction being removed is generated by instruction selection,
so it is part of the original program:

%reg1309<def> = FsMOVLPDrm <fi#4>, 1, %reg0, 0, Mem:LD(8,8) [ZETA + 0]

Since we're hooking up llvm to custom code, I want to check assumptions.
Is there anything in llvm-gcc or the other llvm tools that could generate a
stack slot reference like this before register allocation? Basically, I'm

Codegen can definitely create stack slots during isel lowering. I don't think you can assume all non-fixed slots are created during register allocation.

Evan

Ok, so isn't there a bug in VirtRegMap::RemoveMachineInstrFromMaps since
it assumes every stack index is >= LowSpillSlot, which doesn't get set until
regalloc spill time?

                                               -Dave

Yeah, I think so. It should be pretty simple to fix though. Can you provide a patch? Or please fix a bug.

Evan

Yep, I can provide a patch.

                                              -Dave

Ping. Have you had a chance to address this bug?

Thanks,

Evan

Thanks for the reminder. I just checked it in.

                                  -Dave

Thanks!

Evan