Way to specify instruction latency in itinerary scheduling model

Does anybody know how to specify instruction latency in the itinerary scheduling model? For some reason no matter what I do I get a latency of 1.

From: "Rail Shafigulin via llvm-dev" <llvm-dev@lists.llvm.org>
To: "llvm-dev" <llvm-dev@lists.llvm.org>
Sent: Wednesday, November 11, 2015 6:34:03 PM
Subject: [llvm-dev] Way to specify instruction latency in itinerary scheduling model

Does anybody know how to specify instruction latency in the itinerary
scheduling model? For some reason no matter what I do I get a
latency of 1.

I suspect this is because you're specifying the pipeline structure but not the latencies. For example:

  InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
                                 [72, 0, 0]>,

The '[InstrStage<1, [A2_FU]>]' specifies the pipeline structure (or, here, the first stage of the pipeline), and the '[72, 0, 0]' specifies the operand latencies (output on cycle 72, reads on cycle 0).

-Hal

I suspect this is because you're specifying the pipeline structure but not
the latencies. For example:

  InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
                                 [72, 0, 0]>,

The '[InstrStage<1, [A2_FU]>]' specifies the pipeline structure (or, here,
the first stage of the pipeline), and the '[72, 0, 0]' specifies the
operand latencies (output on cycle 72, reads on cycle 0).

-Hal

--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory

I see. Thank you.