What is the correct sequence of IR instructions to generate subs+sbc pair?

Code Generation AArch64
1

Hi all,

I am struggling to find a sequence of LLVM IR instructions that is eventually lowered to the following sequence:

subs _, x0, x1
sbc  x3, x2, x3

I am using llc -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 -O3.

Interestingly, finding the additive version of this sequence - adds; adc - was easy. Have a look at this: Compiler Explorer

However, the subtraction version doesn’t look easy. I tried this - Compiler Explorer - that faithfully encodes the semantics of subs and sbc in the specification I believe, but it still generates a longish code.

2

sub i128 %0, %1?

There might be some way to get an “sbc” without involving an i128, but not sure what that is off the top of my head. The AArch64 backend basically only generates sbc to lower ISD::SUBCARRY and friends, and DAGCombine currently isn’t that aggressive with carry ops.

1 Like
3

Thanks, indeed using i128 worked :slight_smile: : Compiler Explorer