what is the Line number of Phi Node with addr2line

Hi, all

When compiling a program with -g -O0, and if we have a PC, then with addr2line, we can get the line number of the instruction.

My quesions are: what is the result of Phi node instruction, can we get the similar results ?

Hey Eric,
phi nodes don't exist for real, so you can't.
The are removed by PHI elimination as part of codegen.

What are you trying to achieve?

Hi, Daniel

I want to profile load/store operations, in order to reduce the overhead of profiling, I try to instrument the optimized llvm ir, which has phi nodes.

BTW, when the value of some load/store operations may have multi-source, then the load will be translated into phi nodes, and all phi nodes are placed in the front of BB. Sometimes, the position is not where the load happens, is there any way to figure out where the load should be placed?( If the phi node translated back to load operations)

Best Regards!
Eric Lew

By the way. When I remove these phi nodes with -reg2mem, some new load operations will be inserted, but when I try cache load operations with:
visitFunction
visitLoadInst
It seems we can’t see these new load operations.

Hi, Daniel

I want to profile load/store operations, in order to reduce the overhead of
profiling, I try to instrument the optimized llvm ir, which has phi nodes.

Sure, but if you use -g, it also has debug info metadata attached to
stuff, and will get mostly right answers attached to the output.

BTW, when the value of some load/store operations may have multi-source,
then the load will be translated into phi nodes, and all phi nodes are
placed in the front of BB. Sometimes, the position is not where the load
happens, is there any way to figure out where the load should be placed?( If
the phi node translated back to load operations)

Can you show me a code example, and i can give you an answer on how to
place them :slight_smile:

reg2mem does not eliminate phi nodes the way codegen does, it just
converts ssa values to non-ssa values.

It's not the same thing.

Hey, Daniel

Is it better to instrument in the CodeGen phase ? I am now doing it in the opt phases, and it seems a little complex when instrument phi nodes, because I have to decide where the load operation should be if there are no phi nodes.

%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]

It may load 0 or %indvars.iv.next, I have to add checkLoad(addr, size) in different BBs for different incoming value.

I guess in CodeGen Phase, the code have been changed back to code with load/store already.

Are there examples to show me how to instrument in the CodeGen Phase?

I still don't quite understand why this is hard.
If you are profiling loads/stores, why are you not insetring
instrumentation right before the load/store?

Eric, I think you might be confusing people with your use of the term “load.” In LLVM parlance, “load” means an LLVM load instruction. When an instruction (such as a phi node) uses an SSA register as an operand, we don’t say that it “loads” the value from the SSA register; we say that it “reads” the value of the SSA register. Only the LLVM load instruction “loads” values. The reasoning for this is that SSA registers may be assigned to stack spill slots or to registers, depending upon what the code generator decides. Getting back to your question, it is not clear what you want to do or why you want to do it. If you want to add a call to checkLoad() prior to every memory access that does a read, then all you need to do is to look for all the instructions that read memory (the LLVM load instruction, the atomic instructions, and a few intrinsics like llvm.memcpy()) and insert your call before those instructions. That will allow you to instrument all memory accesses that read memory that are visible at the LLVM IR level. Now, if you want to instrument memory accesses that are not visible at the LLVM IR level (e.g., reads to stack spill slots, pushing parameters on the stack for function calls, etc.), then you need to instrument at the MachineInstr level. These memory access instructions are not visible in the LLVM IR. Hope this helps, John Criswell