What is the meaning of a blank dag selection pattern?

Code Generation Common Infrastructure
#1

In the following instruction format (SPARC example) there are two similar instructions for XNOR shown in the online documentation:

def XNORrr  : F3_1<2, 0b000111,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                   "xnor $rs1, $rs2, $rd",
                   [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
def XNORri  : F3_2<2, 0b000111,
                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                   "xnor $rs1, $simm13, $rd", []>;

Why does only one if these instruction formats contain a dag selection pattern? Or why is the other blank?

What does that mean to have a blank selection pattern?

#2

It’s possible that the instruction is intended to be disabled in codegen for some reason, but still available in assembler / disassembler (i.e. the MC layer)

#3

In addition to what @mshockwave wrote, instruction selection patterns can also be defined as stand-alone TableGen records. We do that a lot in the AMDGPU backend for more complex patterns, e.g. from VOP2Instructions.td:

class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 
  GCNPat<... snip ...>;

def : DivergentBinOp<csrl_32, V_LSHRREV_B32_e64>;
def : DivergentBinOp<csra_32, V_ASHRREV_I32_e64>;
def : DivergentBinOp<cshl_32, V_LSHLREV_B32_e64>;