When I take a look at the function AArch64MIPeepholeOpt::visitORR,it has some comment that the function will check the upper bits of the destination registers are zero.
MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg());
// From https://developer.arm.com/documentation/dui0801/b/BABBGCAC
// When you use the 32-bit form of an instruction, the upper 32 bits of the
// source registers are ignored and the upper 32 bits of the destination
// register are set to zero.
// If AArch64's 32-bit form of instruction defines the source operand of
// zero-extend, we do not need the zero-extend. Let's check the MI's opcode is
// real AArch64 instruction and if it is not, do not process the opcode
if (SrcMI->getOpcode() == TargetOpcode::COPY &&
const TargetRegisterClass *RC =
// A COPY from an FPR will become a FMOVSWr, so do so now so that we know
// that the upper bits are zero.
But I doesn’t see the matched logic, does any guy known where is check of the upper bits?
The check is
SrcMI->getOpcode() <= TargetOpcode::GENERIC_OP_END. We assume any target-specific instruction zeros the high bits of the destination. See
⚙ D110841 [AArch64] Remove redundant ORRWrs which is generated by zero-extend for more.
@efriedma-quic very much.
BTW, does the check
SrcMI->getOpcode() <= TargetOpcode::GENERIC_OP_END depend on the following pattern defined in the backend ? or it is absolutely true for target-specific instruction?
//In the case of a 32-bit def that is known to implicitly zero-extend,
//we can use a SUBREG_TO_REG.
def : Pat<(i64 (zext def32:$src)),
(SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
What version of LLVM are you looking at? We killed off def32 because it was impossible to define correctly. See
⚙ D127154 [AArch64] Remove isDef32 .
Oh, sorry. I just copy the context from the link
above. D110841 [AArch64] Remove redundant ORRWrs which is generated by zero-extend
Yes, it now was killed off.
My understanding is that it’s from
Documentation – Arm Developer (the link in the comment)
When you use the 32-bit form of an instruction, the upper 32 bits of the source registers are ignored and the upper 32 bits of the destination register are set to zero.
Oh, Thanks very much, so it is depended on the register properties, and at least true for AArch64 target.