Writing an LLVM backend documentation example clarification

From Writing an LLVM backend documentation:

`SparcInstrInfo.td` largely consists of operand and instruction definitions for the SPARC target. In 
`SparcInstrInfo.td`, the following target description file entry, `LDrr`, defines the Load Integer instruction 
for a Word (the `LD` SPARC opcode) from a memory address to a register. The first parameter, the value
 3 (`11` 2), is the operation value for this category of operation. The second parameter (`000000` 2) is the
 specific operation value for `LD`/Load Word. The third parameter is the output destination, which is a 
register operand and defined in the `Register` target description file (`IntRegs`).

def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRrr:$addr))]>;

The fourth parameter is the input source, which uses the address operand `MEMrr` that is defined earlier
 in `SparcInstrInfo.td`:

def MEMrr : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops IntRegs, 
IntRegs); }

The fifth parameter is a string that is used by the assembly printer and can be left as an empty string until
 the assembly printer interface is implemented. The sixth and final parameter is the pattern used to match
 the instruction during the SelectionDAG Select Phase described in [The LLVM Target-Independent Code
 Generator](https://llvm.org/docs/CodeGenerator.html). This parameter is detailed in the next section, 
[Instruction Selector](https://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector).

In the example the instruction LDrr loads from a memory address to a register. The second operand being the memory address.

I am struggling to understand the relationship between MEMrr and MIOperandInfo = (ops IntRegs, IntRegs).

What does IntRegs in MIOperandInfo refer to if the operand is expected to be a memory address?

I think I can answer my own question.

From the SPARC 7 assembly language syntax manual. It appears there are two forms of the LD instruction. One that takes two summed registers and one that takes a register summed with an immediate value. Both forms generate an effective memory address.