x86 and GPU backend support for irregular accesses

Hello !

Does the x86 back-end generate gather-scatter instructions for LLVM gather-scatter intrinsics ?

Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions for GPUs ?

Thank You,
Sanjay

Hello !

Does the x86 back-end generate gather-scatter instructions for
LLVM gather-scatter intrinsics ?

Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions
for GPUs ?

Dear Sanjay,

I suggest to just try this out. Create a simple test case and see what
kind of assembly code is generated. Interesting will certainly be the
AVX512 instructions for Xeon PHI.

Best,
Tobias

What do you expect by meaning “equivalent” instructions in NVPTX backend?

Hello Madhur,

I meant any instructions that enable irregular accesses at the hardware level, e.g. a subset of Intel’s AVX 512 and those here.

Thanks,
Sanjay