X86 Code Generation Sign Extension or Register usage

LLVM Project
,
1

In x86 in the code generation how do we choose whether to perform sign extend for a variable of any width as (8, 16, 32) bits or just to insert it into a register for that width?

2

Please can you describe the context more? There are a lot of individual cases: 16-bit ops are usually promoted in the SelectionDAG; others are implicitly promoted through the tablgen isel patterns; ops can be promoted later if they can be incorporated into a LEA instructions etc.

3

I am talking about the Selection DAG optimization phase. The DAGCombiner.

4

You mean that In the SelectionDAG the 16-bit ops are promoted directly to 64 bit values? then where is the usage of 16-bit registers?

5

Sorry, I never saw you replied!

There’s a mixture of places you need to look, its spread out a lot!
e.g.
setOperationAction calls that Promote i16 types
isTypeDesirableForOp avoids creation of i16 ops
X86FixupBWInsts.cpp attempts to promote i8/i16 instructions
etc.