X86 Instructions on LLVM

Hi all,

Just a quick question about X86 instructions inside LLVM. I found it hard to do one-to-one mapping from the instructions in X86GenInstInfo.inc to the instructions in the intel Manual. For example, what instructions are DIVR_F32m and DIVR_F64m mapped to in the intel manual? It would be great if there is some docs about the X86 instructions.

Thanks tons!
Bin

Bin Zeng <ezengbin@gmail.com> writes:

Hi all,

Just a quick question about X86 instructions inside LLVM. I found it
hard to do one-to-one mapping from the instructions in
X86GenInstInfo.inc to the instructions in the intel Manual. For example,
what instructions are DIVR_F32m and DIVR_F64m mapped to in the intel
manual? It would be great if there is some docs about the X86 instructions.

Both map to FDIVR. The suffixes indicate the addressing mode for that
particular pattern:

F32 -> single precision
F64 -> double precision
r -> register
m -> memory
rr -> register-to-register
rm -> memory-to-register (load)
mr -> register-to-memory (store)

So DIVR_F32m is a single-precision reverse divide where the dividend is
from memory and divisor is the top-of-stack. DIVR_F64m is a
double-precision reverse divide with the same addressing mode.

The important thing to know about the X86 codegen is that every
addressing mode variant of an instruction is a separate
MachineInstr/SelectionDAG/etc. opcode. LLVM doesn't have the concept of
"addressing mode," _per_se_. Each combination of addressing modes is a
separate instruction, so there are something like 40 different
instructions for ADD, similar to how they're enumerated in the Intel
manual, except r/m16, etc. are two separate LLVM MachineInstr opcodes,
one with a register operand and one with a memory operand.

                            -Dave