I would like to use the LLVM x86 code generator to emit Intel syntax that is compatible with Microsoft’s MASM 9.x. Taking the TOT LLVM, from last week, I have found a number of changes that are required to make this work, most of which are straight forward but a couple I wanted to check with the group to see what people thought was the best thing to do. In particular, I have made all necessary changes and these are mostly constrained to the files:
X86IntelAsmPrinter.[h|cpp]
X86TargetAsmInfo.[h|cpp]
Making sure the syntax follows Microsoft MASM requirements.
The main problem that I have hit is regarding the use of CL register in the shift instructions. The problem is that ATT syntax states that it should be referenced as “%cl” while Intel says just “cl” but these references occur in X86InstInfo.td and this means that it is shared between Intel and ATT printing! For example, the shift rules:
let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
“shl{b}\t{%cl, $dst|$dst, %CL}”,
[(set GR8:$dst, (shl GR8:$src, %CL))]>;
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
“shl{w}\t{%cl, $dst|$dst, %CL}”,
[(set GR16:$dst, (shl GR16:$src, %CL))]>, OpSize;
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
“shl{l}\t{%cl, $dst|$dst, %CL}”,
[(set GR32:$dst, (shl GR32:$src, %CL))]>;
} // Uses = [CL]
Needs to be:
let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
“shl{b}\t{%cl, $dst|$dst, CL}”,
[(set GR8:$dst, (shl GR8:$src, CL))]>;
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
“shl{w}\t{%cl, $dst|$dst, CL}”,
[(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
“shl{l}\t{%cl, $dst|$dst, CL}”,
[(set GR32:$dst, (shl GR32:$src, CL))]>;
} // Uses = [CL]
The problem is that it does not make sense to have separate rules for Intel and ATT and as such I wanted to get the lists advice on what people think is the best approach to resolving this issue so I can make the changes?
It is also worth noting that MASM does not allow:
shr ESI
to be mean shift by 1 and instead I have to emit:
shr ESI, 1
which I’m assuming is not an issue?
Finally, as far as I can tell from comments on the mailing list the current Intel syntax emitted by LLVM does not work with any particular Window’s assembler and so making these changes will not cause another path to stop working, is this correct?
Many thanks,
Ben
if you knew of a better method to handling this?