I think there's a bug somewhere in TableGen for the X86 disassembler
emitter. The following test:
$ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble
.section __TEXT,__text,regular,pure_instructions
movsd
(from llvm trunk)
0xF3 is the REP prefix, so the printed instruction should be 'rep
movsd', however all that is printed is 'movsd'. It seems that there is
an instruction enum for REP_MOVSD, but it isn't emitted in the
generated .inc file? Is this a bug/oversight, or is there something I
don't understand about the instruction decoding infrastructure and the
MCInst class?