Hi all,

what is exactly “zero_reg”?


def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {…}

I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable.

Can someone please give me more information about zero_reg and if possible more about PredicateOperand operands.



This corresponds to NoRegister (this could use a rename). It allows you to emit an operand an an instruction pattern with an invalid register value which presumably something else expects to fill in later.

Oh, thanks a lot Matt. :slight_smile: