[RFC] Desugar variadics. Codegen for new targets, optimisation for existing
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4
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372
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November 16, 2023
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Confused by inconsistencies in GPU magic constants
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19
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532
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September 18, 2023
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InferAddrSpace] The operand with non-FLAT-address-space got Undefined when rewriting its user to new address space
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28
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422
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September 4, 2023
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The value of a constant global variable is random after linking for AMDGPU
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0
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145
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July 18, 2023
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[RFC] Cleaning up the NVIDIA (and potentially AMD) GPU backend
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5
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389
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June 29, 2023
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Loop unroller fails to unroll loop
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5
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451
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April 12, 2023
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Catching up on uniformity analysis
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5
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294
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February 13, 2023
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Convert NVIDIA GPU LLVM IR(NVVM) alloca instruction to AMDGPU's
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7
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747
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September 9, 2022
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[TableGen/RegAlloc] How to use a fixed register in an instruction?
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5
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536
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August 16, 2022
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[GISel/DAG] Getting a TableGen pattern to match both `G_ADD` and `G_PTR_ADD` in GISel
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0
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200
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August 12, 2022
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Feedback on new flag for AMDGPU
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4
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308
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February 22, 2022
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