[ABI] Does it different with/without aarch64_vector_pcs for sve

Beginners
1

hi,
According the standard ABI for vector routines is defined here:
https://github.com/ARM-software/abi-aa/releases/download/2021Q3/vfabia64.pdf.

   For user-defined SVE vector functions the attribute is not required as AAPCS and AAVPCS are equivalent.

so I expect the _ZGVnN2v_acosh and _ZGVnN2v_acosh1 in the follow defining generate same assemble, but now it is not. Do I missing some things ?

define aarch64_vector_pcs <vscale x 2 x double> @_ZGVnN2v_acosh() {
  %call = call double @acosh()
  ret <vscale x 2 x double> zeroinitializer
}

define <vscale x 2 x double> @_ZGVnN2v_acosh1() {
  %call = call double @acosh()
  ret <vscale x 2 x double> zeroinitializer
}
2

There’s a separate aarch64_sve_vector_pcs which is applied by default to _ZGVnN2v_acosh1, since you’re returning a scalable vector. However, you’ve overridden that to aarch64_vector_pcs for _ZGVnN2v_acosh, which only guarantees that NEON/ASIMD registers are preserved instead of SVE registers.

1 Like
3

Thanks very much