Hi Tom,
Thanks for your response. The sample code that I was compiling just have 1 loop in it and interestingly this issue only occurs if I run some combination of passes on the .ll code(when running both loop strength reduce and SROA, it doesnt happen if I run one or the other). The following is the machine function dump of the code:
BB#10: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#9 BB#12
%reg1039<def> = MOV %reg1099
%reg1040<def> = MOV %reg1100
%reg1041<def> = MOV %reg1101
%reg1042<def> = MOV %reg1102
%reg1043<def> = MOV %reg1103
%reg1044<def> = MOV %reg1104
%reg1080<def> = FADD_RR %reg1042, %reg1043
%reg1081<def> = CMP_F32_UGT %reg1080, %reg1038
IF %reg1081, <BB#13>
Successors according to CFG: BB#14 BB#13
BB#14: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#10
%reg1082<def> = CMP_I32_UGE %reg1044, %reg1026
IF %reg1082, <BB#13>
Successors according to CFG: BB#11 BB#13
BB#11: derived from LLVM BB %for.body
Predecessors according to CFG: BB#14
%reg1083<def> = FADD %reg1040, %reg1040
%reg1048<def> = MOV %reg1083
Successors according to CFG: BB#12
BB#12: derived from LLVM BB %for.inc
Predecessors according to CFG: BB#11
%reg1090<def> = ADD %reg1044, 1
%reg1091<def> = ADD %reg1039, 255
%reg1049<def> = MOV %reg1090
%reg1050<def> = MOV %reg1091
UncondBr <BB#10>
%reg1099<def> = MOV %reg1050
%reg1100<def> = MOV %reg1046
%reg1101<def> = MOV %reg1045
%reg1102<def> = MOV %reg1047
%reg1103<def> = MOV %reg1048
%reg1104<def> = MOV %reg1049
Successors according to CFG: BB#10
BB#13: derived from LLVM BB %for.end
Predecessors according to CFG: BB#10 BB#14
%reg1095<def> = ADD %reg1024, %reg1092
STORE %reg1048, %reg1095; mem:ST4[%arrayidx]
return
for the above code its returning true for both BB10 and BB14. but, instead if i use getLoopHdr for the same set of blocks, i get the right result(both blocks returns the same hdr = #BB10).
Thanks for help,
Hisham