Disassemble register of which TableGen Inst field does not contain its register encoding

Hello.

I’m wondering how to handle the case on Disassembler when the registers used in an instruction are fixed, but the registers need to be specified in AsmString.

For example, suppose there is a MOV instruction that moves from any register to the A register. In this case, AsmString is MOV A, X.
The source register is arbitrary, so the register information is included in the instruction, but the destination register is fixed at A, so no information is included in the instruction. In this case, the Inst field specified in TableGen’s Instruction class does not contain the A register information, so the Disassembler does not decode the A register info, and MCInst A register operand information is missing. As a result, the program (llvm-objdump) crashes when MCInstPrinter’s printOperand attempts to output more operands than there are in MCInst.

If the register is not in AsmString, it can be handled by using Defs/Uses, but This cannot apply in this case.

I tried writing AsmString, A, $src, but this resulted in a syntax error as the number of operands did not match. This is because AsmParser parsed A as a register operand. AsmParser parses A in the assembly code as a register, and A and $src exist as operands. On the other hand, AsmString would expect $src will be the only operand.

I tried a workaround, adding a dummy space in the Inst field for A register, and it seems to work.
As a example, using above MOV instruction definition,

// [6X] MOV A, r
def MOV_A_r : MOV<(outs AReg:$dst), (ins GPR:$src), "$dst, $src"> {
  bits<3> src;
  bits<3> dst;
  
  // change bits<8> into bits<11>, added 3bit is dummy space;
  bits<11> Inst;                  

  let Size = 1;            // In actual, this instr is 1byte length 

  let Inst{10-8} = dst;    // Insert reg encoding into dummy Inst space
  let Inst{7-4} = 0x6;
  let Inst{3}   = 0;
  let Inst{2-0} = src;
}

However, is this a fragile method? i.e. this may be non intended behavior, and causing unexpected result depending on the situation?