Hello
I think I found a bug in the x86 instruction definition file, while trying out the disassembler.
It looks like the “ADD32rr_alt” instruction should have GR32 operands, not GR16.
Attached you can find a patch, which should fix the problem.
But even with the change I can not decode e.g. “0x03 0xC1” (should be “addl %ecx, %eax”) only if I remove the “isCodeGenOnly = 1” line it works.
Looking for help.
– Marius Wachtler
fix_ADD32rr_alt_enc.diff (647 Bytes)