Hi all,
I am new to llvm. I need help. Thank you every!
I want to realize vcvtt.f16.f32 NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc , I meet is following problem :
Can you show us the command line you are using? At least can you tell us the backend you tried on? If you can upload the test case as well, it will be very useful to find out the problem.
Thank you Kevin!!!
If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, “fptrunc double %tmp to float” is right, but “fptrunc float %tmp to half” is wrong). My target platform is MIPS. The command as following:
NEON:
vcvtt.f16.f32 s2, s0
llvm Code:
%Vt_2 = load float* %VFP_s0, align 4
%Vt3_1 = fptrunc float %Vt_2 to half
%Vt4_1 = bitcast half %Vt3_1 to i16
%Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>*
%Vrti_1 = load <2 x i16>* %Vt2_2, align 4
%Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1
%Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>*
store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4
AFAIK, MIPS doesn't support NEON. But that doesn't explain your
problem, which is probably due to hand-crafted IR.
Can you provide the full IR, with header and everything? Also the
command line that you're using with the LLVM tool you're using to
compile (llc?lli?).
It'd also be good to know how you generated that IR in the frist
place. Was it a tool? A front-end? Hand-crafted?
NEON is an ARM feature and is therefore not supported by MIPS so I assume you are trying to achieve the same effect. As far as I know, the MIPS backend doesn’t support half-precision floating point at the moment.
There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported.
I think that support for the half type is only implemented for ARM. Last I tried to use it, I found that none of it works even on x86, and the current handling of the half conversion SDNodes seem to rely on ARM specific assumptions
Not sure if this can help, but
if you really really want to have minimal half float support on Mips,
then one thing you could try to do is to hack MipsISelLowering.cpp
adding rules to expand float-half conversion SDNodes into library
calls.
(The MVT::i32 on the second rule is required because type i16 is
promoted to i32).
If you then convert every occurrence of 'fptrunc' from float to half
with calls to @llvm.convert.to.fp16, then you should be able to
compile (hopefully) with no errors.
That means, in your original example you would convert the following
IR statement:
%Vt3_1 = fptrunc float %Vt_2 to half
into
%Vt3_1 = call i16 @llvm.convert.to.fp16(float %Vt_2)
The downside is that you will have to add definitions for
'__gnu_f2h_ieee' and '__gnu_h2f_ieee' in the compiler runtime. That is
because the backend will expand all the float-half conversions into
library calls...
This workaround should work assuming that a) you can hack the backend,
and b) it is acceptable (i.e. a reasonable solution in your case) to
have a library call for every float-half conversion in your code.
I think that support for the half type is only implemented for ARM. Last I
tried to use it, I found that none of it works even on x86, and the current
handling of the half conversion SDNodes seem to rely on ARM specific
assumptions
Just for the record,
since revision 212293 (committed only five days ago), the x86 backend
supports float half conversions.
On x86, if the target has F16C, there are ISel patterns to map
float-half conversions to specific instructions. If there is no F16C
support, then the backend expands float-half conversions into runtime
library calls.
Hi Renato,
Thank you your replying.
Yes, we are making a tool in order to generate MIPS IR by ARM asembler. The ir is Hand-crafted. We want to realise NEON instruction “vcvtt.f16.f32” by llvm.
Yes, MIPS is not supported NEON, but the problem is not related with mips platform. I think this problem only relate with llc of llvm, so this problem is about convertion between half float and float. The problem I don’t understand is if llvm support half float, how to convert float to half float.
NEON is an ARM feature and is therefore not supported by MIPS so I assume you are trying to achieve the same effect. As far as I know, the MIPS backend doesn’t support half-precision floating point at the moment.
There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported.
For the implementation, search for ‘addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);’ in lib/Target/Mips/MipsSEISelLowering.cpp. Most operations are expanded but it supports ISD::LOAD, ISD::STORE, ISD::BITCAST, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, BUILD_VECTOR, and a couple intrinsics. In MipsMSAInstrInto.td, you can also search for FEXDO_H, FEXUPL_W, and FEXUPR_W which are the only operations that use v8f16. There is no reference to the ‘f16’ type in the Mips backend so scalars are not implemented.
Hi Matt,
Thank you your replying. I try to use @llvm.convert.to/from.fp16 intrinsics before, I also meet “LLVM ERROR: Cannot select: fp32_to_fp16” problem, maybe these functions call fptrunc/fpext. Following is detail log:
For the implementation, search for ‘addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);’ in lib/Target/Mips/MipsSEISelLowering.cpp. Most operations are expanded but it supports ISD::LOAD, ISD::STORE, ISD::BITCAST, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, BUILD_VECTOR, and a couple intrinsics. In MipsMSAInstrInto.td, you can also search for FEXDO_H, FEXUPL_W, and FEXUPR_W which are the only operations that use v8f16. There is no reference to the ‘f16’ type in the Mips backend so scalars are not implemented.
Hi Andrea
Thank you your replying.
I do like your letter. Add following to line to MipsISelLowering.cpp. As your words, @llvm.convert.to.fp16 can compile successfully. However, the runtime is not right.