Help request: Output reshuffling

OK I managed to make some progress on this, by using a MergeValues node:

     SDNode* LDW = CurDAG->getMachineNode(
       AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other,
       LD->getBasePtr(), LD->getChain());
     SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2) };
     SDNode* NN = CurDAG->getMergeValues(Unpack, SDLoc(N)).getNode();

     ReplaceNode(N, NN);

which gets me from

t17: i16,ch = load<LD2[%v25](align=1)(dereferenceable)> t16:1, t2, undef:i16


t24: i16,i16,ch = LDWRdPtr t2, t16:1

looking tood; but then it fails during scheduling with

llc: CodeGen/SelectionDAG/InstrEmitter.cpp:303: unsigned int llvm::InstrEmitter::getVR(
   llvm::DenseMap<llvm::SDValue, unsigned int>&):
Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed.

Looking at the result of selection again, I now noticed that here:

t26: i16,i16,ch = LDWRdPtr t2, t0
t27: i16,ch = merge_values t26, t26:2

I'm not sure what that t26:2 means, and why it's not

t27: i16,ch = merge_values t26, ch

Could that be a hint to what's going wrong?


I’m still completely stuck on this one. To recap, during instruction selection, I’m trying to use something of type (i16, i16, ch) as the selection for an instruction which has type (i16, ch) by not using the second i16 returned. Using getMergeValues I created something that almost looks right, but fails scheduling; my suspicion is that it doesn’t tunnel the ch result through properly.