Live Interval Analysis and pipelining.

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1

Hi,

I’m writing a backend for a proprietary microcontroller.

I’m facing a limitation related to Live Interval Analysis.

Some FPU instructions, most notably the FDIV, requires a few cycles to complete.

There is a pipeline and, during the execution of the FDIV, others instructions could be executed in parallel, provided they don’t use the same registers.

This pipeline has been modeled for the instruction scheduling through SchedMachineModel and ProcessorItineraries in .td file.

My problem is that the Live Interval Analysis seems to be over optimistic. It consider that the interval is closed when the FPU instruction start, not when it is completed.

With such analysis it reallocate a physical register to early, while still used by the FPU instruction, which compromises the FPU result.

Is there a mechanism (.td scheduling model or C++ hook) to extend the live analysis range in order to cover the pipeline execution?

Thanks in advance, Dominique Torette.

2

Hi,
Live interval analysis represents a certain model of data flow, not the actual hardware behavior. The model is such that the last register use (for a given definition) ends the live segment for that register.
Dealing with the hardware behavior is left to the schedulers. In particular, targets can provide their of hazard recognizers to aid the scheduling (see the ScheduleHazardRecognizer class).

-Krzysztof