LLVM backends instruction selection

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1

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc.

Thanks

2

Hi, Xin

I am new to the LLVM backends, I am wondering how instruction selection is
done in LLVM backends, I looked at the .td files in Target/X86, they all
seem to be small and do not deal with common X86 instructions, i.e. mov,
push, pop, etc.

  Have you read The LLVM Target-Independent Code Generator — LLVM 18.0.0git documentation ? I also find
this slide helps http://reup.dmcs.pl/wiki/images/7/7a/Tricore-llvm-slides.pdf .

HTH.

Regards,
chenwj

3

I am new to the LLVM backends, I am wondering how instruction selection is done
in LLVM backends, I looked at the .td files in Target/X86, they all seem to be
small and do not deal with common X86 instructions, i.e. mov, push, pop, etc.

$ grep pop lib/Target/X86/*.td
lib/Target/X86/X86.td:def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
lib/Target/X86/X86InstrCompiler.td:// popl %destreg"
lib/Target/X86/X86InstrFPStack.td:def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
lib/Target/X86/X86InstrFPStack.td:def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
lib/Target/X86/X86InstrFPStack.td:def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
lib/Target/X86/X86InstrInfo.td:// after callee-saved register are popped.
lib/Target/X86/X86InstrInfo.td:def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", >,
lib/Target/X86/X86InstrInfo.td:def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", >;
lib/Target/X86/X86InstrInfo.td:def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", >,
lib/Target/X86/X86InstrInfo.td:def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", >,
lib/Target/X86/X86InstrInfo.td:def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", >;
lib/Target/X86/X86InstrInfo.td:def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", >;
lib/Target/X86/X86InstrInfo.td:def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", >, OpSize;
lib/Target/X86/X86InstrInfo.td:def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", >,
lib/Target/X86/X86InstrInfo.td: (outs GR64:$reg), (ins), "pop{q}\t$reg", >;
lib/Target/X86/X86InstrInfo.td:def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", >;
lib/Target/X86/X86InstrInfo.td:def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", >;
lib/Target/X86/X86InstrInfo.td:def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", >,
lib/Target/X86/X86InstrInfo.td:def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", >,
lib/Target/X86/X86InstrInfo.td:def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
lib/Target/X86/X86InstrInfo.td:def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
lib/Target/X86/X86InstrInfo.td:def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
lib/Target/X86/X86InstrInfo.td:def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
lib/Target/X86/X86InstrInfo.td:def : MnemonicAlias<"popfd", "popfl">;
lib/Target/X86/X86InstrInfo.td:// pushl/pushq depending on the current mode. Similar for "pop %bx"
lib/Target/X86/X86InstrSSE.td: "popcnt{w}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
lib/Target/X86/X86InstrSSE.td: "popcnt{w}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
lib/Target/X86/X86InstrSSE.td: "popcnt{l}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
lib/Target/X86/X86InstrSSE.td: "popcnt{l}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
lib/Target/X86/X86InstrSSE.td: "popcnt{q}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
lib/Target/X86/X86InstrSSE.td: "popcnt{q}\t{$src, $dst|$dst, $src}",
lib/Target/X86/X86InstrSSE.td: [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
lib/Target/X86/X86InstrSystem.td:// No "pop cs" instruction.
lib/Target/X86/X86InstrSystem.td: "pop{w}\t{%ss|SS}", >, OpSize, Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{l}\t{%ss|SS}", > , Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{w}\t{%ds|DS}", >, OpSize, Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{l}\t{%ds|DS}", > , Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{w}\t{%es|ES}", >, OpSize, Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{l}\t{%es|ES}", > , Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{w}\t{%fs|FS}", >, OpSize, TB;
lib/Target/X86/X86InstrSystem.td: "pop{l}\t{%fs|FS}", >, TB , Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{q}\t{%fs|FS}", >, TB;
lib/Target/X86/X86InstrSystem.td: "pop{w}\t{%gs|GS}", >, OpSize, TB;
lib/Target/X86/X86InstrSystem.td: "pop{l}\t{%gs|GS}", >, TB , Requires<[In32BitMode]>;
lib/Target/X86/X86InstrSystem.td: "pop{q}\t{%gs|GS}", >, TB;