LLVM MAYbeAllign

Beginners
1

I was working on creating a new instruction in the existing IR, i.e., an atomic addition using CreateAtomicRMW(). In the llvm docmentation, CreateAtomicRMW takes the foillowing parameters:

CreateAtomicRMW (AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val, MaybeAlign Align, AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System)

I’m confused regrading the last 3 parameters, MaybeAlign, ordering and SyncScope.
The source code of CreateAtomicRMW is following:

AtomicRMWInst *CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr,
                                 Value *Val, MaybeAlign Align,
                                 AtomicOrdering Ordering,
                                 SyncScope::ID SSID = SyncScope::System) {
    if (!Align) {
      const DataLayout &DL = BB->getModule()->getDataLayout();
      Align = llvm::Align(DL.getTypeStoreSize(Val->getType()));
    }
 
    return Insert(new AtomicRMWInst(Op, Ptr, Val, *Align, Ordering, SSID));
  }

So here instead of align, I’m passing null pointer but it gives me error. It only works if I pass a MaybeAlign object to it. So basically what is this MaybeAlign and why is it required for creating atomic instruction?
Secondly, the atomic ordering class has the following declaration:

enum class AtomicOrdering : unsigned {
  NotAtomic = 0,
  Unordered = 1,
  Monotonic = 2, // Equivalent to C++'s relaxed.
  // Consume = 3,  // Not specified yet.
  Acquire = 4,
  Release = 5,
  AcquireRelease = 6,
  SequentiallyConsistent = 7,
  LAST = SequentiallyConsistent
};

Can someone please guide me to a usefull resource from where I can understand these orderings.

2

These atomic instructions will read and write memory. The “Align” parameter states what the address alignment is. On some architectures memory instructions have specific alignment requirements, so the compiler needs to know the least guaranteed alignment to generate an appropriate instruction.

The different types of orderings describe how loads/stores from one processor are ordered with respect to loads/stores from other processors that happen at around the same time. There are many sources on that, see Wikipedia for example: Consistency model - Wikipedia.