LLVM Weekly - #488, May 8th 2023

LLVM Weekly - #488, May 8th 2023

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Welcome to the four hundred and eighty-eighth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at http://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, @llvmweekly or @asbradbury on Twitter, or @llvmweekly@fosstodon.org or @asb@fosstodon.org.

News and articles from around the web and events

LLVM 16.0.3 was released.

The next LLVM Bay Area Meetup will take place on Mon May 29th.

Mojo, a new higher performance Python-superset language leveraging MLIR in its implementation has been announced by Modular.

EuroLLVM is taking place this week May 10-11 in Glasgow. Looking forward to seeing a number of you there! There’s also now a Discord channel for attendees.

A Clang-Built Linux meetup is planned for 11th November in Richmond VA, close to the Linux Plumbers Conference. More details will be posted soon.

According to the LLVM calendar in the coming week there will be:

  • Office hours with the following hosts: Aaron Ballman, Alexey Bader, Alina Sbirlea, Johannes Doerfert, BOLT devs.
  • Online sync-ups on the following topics: OpenMP, MLIR, SPIR-V.
  • For more details see the LLVM calendar, getting involved documentation on online sync ups and office hours.

On the forums

LLVM commits

  • llvm/CodeGen/MachineValueType.h is now generated from ValueTypes.td. 631bfdb.

  • A PerThreadBumpPtrAllocator class was added to Support. 6ab43f9.

  • Support for the compact binary sample profile format was removed. d38d6ca.

  • MC layer support for decimal floating point add and subtract instructions was added to the PowerPC backend. c74aec9.

  • Support for the experimental ‘Smaia’ and ‘Ssaia’ extensions was added to the RISC-V backend. This introduces new CSRs used by the Advanced Interrupt Architecture (AIA). 74c1fa6.

  • Codegen for the Zfinx and Zdinx (on RV64 only for now) extensions (floating point using general purpose registers) on RISC-V. fe558ef, 2dc0fa0.

  • Datalayout entries were added for buffer resources (address space 8) on AMDGPU. f9c1ede.

  • The policy around branches on GitHub was documented. ead5024.

  • The AArch64 peephole optimisation to remove instructions that redundantly zero the top half of a register was taught that this can be done for all instructions defining an FPR64 register. 6e7840d.

Clang commits

  • Now C++23 has been voted as technically complete, -std=c++23 is now used rather than -std=c++2b. ba15d18.

  • clang-tidy gained a bugprone-multiple-new-in-one-expression check. 1aa36da.

  • RenamerClangTidyCheck performance was improved. The commit message reports 72% reduced execution time for bugprone-reserved-identifier. 1c28205.

  • C intrinsics for the RISC-V vendor-specific Xsfvcp extension are now supported. 8ed9cf0.

  • Several issues with C++ MS ABI mangling were fixed. cd93532.

Other project commits

  • MLIR operation properties were introduced. This can be used as an alternative to attributes to store data specific to an operation. d572cd1.

  • LLVM’s libc gained the socket function. ee17fd7.

  • LLVM libc on GPU can now have multiple threads using RPC, and allows concurrent RPC port access. 507edb5, aea866c.

  • A short design doc on PSTL integration was added to libcxx and the PSTL is now available by default under -fexperimental-library. 5c6be1d.

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