The simplest thing to do is to map a vector_shuffle to another
vector_shuffle; there shouldn't be any issues with that, I think. Is
there some reason you don't want to write it that way?
Note that you can use a custom PatFrag to match an instruction with a
single use... see, for example, "and_su" in X86InstrInfo.td.
into "four" different machines instructions, respectively:
MUL_AND
ADD_AND
SUB_AND
UDIV_AND
That is, this machine is capable of doing an arithmetic operation and a
"following" AND operation by a single machine instruction. There are a lot
of arithmetic operations but they can only be combined with a following AND
operation. It's important that only the following AND can be merged/combined
with the arithmetic operation. The pattern:
(mul node:$val0, (AND))
can _not_ be matched.
The problem is, it seems to me, that the instruction returned in these
patterns is always the AND, which is the "root" of these partial DAG
pattern, instead of the arithmetic operation. The LLVM instruction selector
is capable of doing this "look ahead" matching? What is the suggested way to
do this?
PS: For GPU guys, I am trying to match the writemask operation after an
arithmetic operation.