See the previous published edition.
Welcome to the nineteenth issue of the MLIR (bi)Weekly, a newsletter (published on Friday) covering developments in MLIR, and related projects in the ecosystem. MLIR (bi)Weekly is brought to you by a collective effort of contributors, we welcome your contributions!
- Impressive progress on the sparse code generation work (TACO-style codegen in MLIR)
- Interesting blog post about using MLIR for Verona (see below)
- The Python bindings (and the underlying C bindings) are making progress, pending more comprehensive examples you can skim the unit-tests. We support now expressing the MLIRContext, Location, and InsertionPoint through python context. @stellaraccident is looking for help around packaging / releasing / Conda recipes / testing on Mac and Windows /…, please volunteer!
- The deprecated global dialect registration has been removed.
- The applyPatternsAndFoldGreedily methods have been moved to Transforms along with some additional pattern restructuring.
- New walkers have been added to walk Blocks and Regions.
- Attribute/Type ASM alias specification has been greatly simplified, allowing for dialects to more easily provide aliases.
- The Inliner now has an additional legality hook specifically for calls/callables, and now propagates whether the callable will be cloned during inlining or not.
attr-dictmay now be specified in a custom directive of the declarative op assembly format.
- A new FrozenRewritePatternList class has been added to represent a pattern list that is fully compiled and ready for application. (This is now the API used by all pattern drivers).
- A new conversion pass has been added to convert from PDL to the PDL interpreter dialect.
- Initial version of tileAndFuse on tensors has landed, future improvements will wait for bufferization post-transformations on Linalg on tensors.
- Initial version of tileAndDistribute on tensors [sent for review](](https://reviews.llvm.org/D90475), future improvements will wait for bufferization post-transformations on Linalg on tensors.
- Work has started on bufferization post-transformations on Linalg on tensors.
- [CPU] A lot of progress on sparse tensor support in MLIR, starting from annotated Linalg:
- All "pseudo code generation” completed, including optimizations
- Output matches TACO generated samples exactly
- Actual MLIR codegen is almost done, pending while-loop support
- Current version “bufferizes” locally, since we don’t have global sparse types (yet)
- First patch with various 1-D, 2-D, and 3-D tensor unit tests is expected next week
- Initial support for SPIR-V module combination is landed. It can merge contents from multiple spv.module into one.
- The SPIR-V CPU runner is landed (last bit of GSOC project). It converts SPIR-V into LLVM and runs it on the CPU.
IREE : An Experimental MLIR Execution Environment
- Add a mechanism to benchmark executable dispatch functions.
mlir-npcomp: Prototype for compiling numpy programs
- functionality for tracing PyTorch programs into
atendialect is starting to come together. (basic conv + NLLLoss is working, tracing backward pass still has bugs)
- most bufferization components have been upstreamed / are in the process of being upstreamed.
- Migrated XLA/GPU emitters to take MLIR LMHLO FusionOp for all loop fusions.
CIRCT : Circuit IR Compilers and Tools aka ‘MLIR for hardware’
- A number of patches related to modeling external modules in verilog have landed.
- Support for FIRRTL verification statements and lowering to LLVM has landed
- Support for representing RTL outputs as result values has landed
- First parts of ESI dialect have landed.
- Tests infrastructure using Verilator has landed.
- 2020-10-22: Fusion of Elementwise operations with Linalg on tensors ; slides - recording
- 2020-10-29: Using MLIR for Multi-Dimensional Homomorphism ; slides - recording
In this blog post, @rengolin introduces Verona at a high-level and provide some motivation and insights in its use of MLIR. Don’t miss the call for contributions!