[RFC] Add RISC-V Vector Extension (RVV) Dialect

MLIR
32

Update

Here is the current RISCVV dialect patch .

Integration Test

  • Build the integration test environment

Currently, there is no RVV hardware available, so the emulator is required for the integration tests. I provide an environment setup document to show how to build the toolchain and perform the integration tests.

  • Test cases

I add three cases for the integration tests.

  1. test-riscvv-arithmetic
  2. test-riscvv-memory
  3. test-riscvv-stripmining

Patterns for the mask/tail policy strategies

There are two strategies to control the mask/tail policy in the RISC-V LLVM IR intrinsics:

  1. Use the “policy” argument at the end of the argument list.
  2. Use the “passthrough” argument at the beginning of the argument list.

I add two patterns (“ConvertPolicyOperandOpToLLVMPattern” and “ConvertPassthruOperandOpToLLVMPattern”) to deal with these two strategies.

Discussion

  • Unified integration test configurations for the emulator

The emulator configurations for the integration test are target specific. So I use similar configurations for the RVV side now, but it seems a little cumbersome. Should we design unified configurations for the integration test with emulators?

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