As per the suggestions on this thread and the reviews posted earlier, we implemented a target specific solution. Instead of a new generic PRED_COPY opcode, we now have an AMDGPU::PRED_COPY opcode which we intend to use for WholeWaveMode(WWM) copy operations.
For now, our primary objective is to use this opcode instead of TARGET_OPCODE::COPY for live range splitting in regalloc which will allow us to construct appropriate MIR for these WWM operations.
The solution involves modifying relevant copy checks in the register allocator pipeline(LiveRangeSplitting.cpp, InlineSpiller, TII::foldMemoryOperand, etc) so that this new PRED_COPY is still recognized as a COPY. Achieved by replacing MI.isCopy() checks with TII.isCopyInstr(MI) allowing targets to query if MI is a copy instruction.
There is a major issue that we are facing with this. TII.isCopyInstr() is interpreted very differently by targets, for example in MIPS it returns true for “WRDSP %0:gpr32, 16, implicit-def $dspccond” and since COPY is considered to be within registers the immediate operand here causes the compiler to crash. Moreover, now a wider set of instructions are queried as copies in the register allocator. Some x86 tests also required updating after this but I think they are okay [D150388]. Shouldn’t these target implementations be revised?
Requesting review comments from MIPS, X86, Thumb2 target experts.
WIP patches: [D150388, D150390]
edit: MIPS test crashing after D150388 : CodeGen/Mips/dsp-r1.ll