RFC: New intrinsics masked.expandload and masked.compressstore

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1

Hi all,

AVX-512 ISA introduces new vector instructions VCOMPRESS and VEXPAND in order to allow vectorization of the following loops with two specific types of cross-iteration dependencies:

Compress:
for (int i=0; i<N; ++i)
If (t[i])
*A++ = expr;

Expand:
for (i=0; i<N; ++i)
If (t[i])
X[i] = *A++;
else
X[i] = PassThruV[i];

On this poster ( http://llvm.org/devmtg/2013-11/slides/Demikhovsky-Poster.pdf ) you’ll find depicted “compress” and “expand” patterns.

The RFC proposes to support this functionality by introducing two intrinsics to LLVM IR:
llvm.masked.expandload.*
llvm.masked.compressstore.*

The syntax of these two intrinsics is similar to the syntax of llvm.masked.load.* and masked.store.*, respectively, but the semantics are different, matching the above patterns.

%res = call <16 x float> @llvm.masked.expandload.v16f32.p0f32 (float* %ptr, <16 x i1>%mask, <16 x float> %passthru)
void @llvm.masked.compressstore.v16f32.p0f32 (<16 x float> , float* , <16 x i1> )

The arguments - %mask, %value and %passthru all have the same vector length.
The underlying type of %ptr corresponds to the scalar type of the vector value.
(In brief; the full syntax description will be provided in subsequent full documentation.)

The intrinsics are planned to be target independent, similar to masked.load/store/gather/scatter. They will be lowered effectively on AVX-512 and scalarized on other targets, also akin to masked.* intrinsics.
Loop vectorizer will query TTI about existence of effective support for these intrinsics, and if provided will be able to handle loops with such cross-iteration dependences.

The first step will include the full documentation and implementation of CodeGen part.

An additional information about expand load ( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=expandload&techs=AVX_512 ) and compress store (https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=compressstore&techs=AVX_512 ) you also can find in the Intel Intrinsic Guide.

  • Elena
2

Hi Elena,

Technically speaking, this seems straightforward.

I wonder, however, how target-independent this is in a practical sense; will there be an efficient lowering when targeting any other ISA? I don't want to get into the territory where, because the vectorizer is supposed to be architecture independent, we need to add target-independent intrinsics for all potentially-side-effect-carrying idioms (or just complicated idioms) we want the vectorizer to support on any target. Is there a way we can design the vectorizer so that the targets can plug in their own idiom recognition for these kinds of things, and then, via that interface, let the vectorizer produce the relevant target-dependent intrinsics?

Thanks again,
Hal

3

  >Hi Elena,
  >
  >Technically speaking, this seems straightforward.
  >
  >I wonder, however, how target-independent this is in a practical
  >sense; will there be an efficient lowering when targeting any other
  >ISA? I don't want to get into the territory where, because the
  >vectorizer is supposed to be architecture independent, we need to
  >add target-independent intrinsics for all potentially-side-effect-
  >carrying idioms (or just complicated idioms) we want the vectorizer to
  >support on any target. Is there a way we can design the vectorizer so
  >that the targets can plug in their own idiom recognition for these
  >kinds of things, and then, via that interface, let the vectorizer produce
  >the relevant target-dependent intrinsics?

Entering target specific plug-in in vectorizer may be a good idea. We need target specific pattern recognition and target specific implementation of “vectorizeMemoryInstruction”. (It may be more functionality in the future)
TTI->checkAdditionalVectorizationOppotunities() - detects target specific patterns; X86 will find compress/expand and may be others
TTI->vectorizeMemoryInstruction() - handle only exotic target-specific cases

Pros:
It will allow us to implement all X86 specific solutions.
The expandload and compresssrore intrinsics may be x86 specific, polymorphic:
llvm.x86.masked.expandload()
llvm.x86.masked.compressstore()

Cons:

TTI will need to deal with Loop Info, SCEVs and other loop analysis info that it does not have today. (I do not like this way)
Or we'll need to introduce TLV - Target Loop Vectorizer - a new class that handles all target specific cases. This solution seems more reasonable, but too heavy just for compress/expand.
Do you see any other target plug-in solution?

-Elena

4

In theory, we could offload several things to such a target plug-in, I’m just not entirely sure we want to.

Two examples I can think of:

  1. This could be a better interface for masked load/stores and gathers.

  2. Horizontal reductions. I tried writing yet-another-horizontals-as-first-class-citizens proposal a couple of months ago, and the main problem from the previous discussions about this was that there’s no good common representation. E.g. should a horizontal add return a vector or a scalar, should it return the base type of the vector (assumes saturation) or a wider integer type, etc. With a plugin, we could have the vectorizer emit the right target intrinsic, instead of the crazy backend pattern-matching we have now.

5

We also may want to implement strided memory access on X86, masking allows to do this safely.

One day we’ll need to mask FP operations as a part of FP exception mode.

Arithmetic operations with saturation.

  • Elena
6

From: "Elena Demikhovsky" <elena.demikhovsky@intel.com>
To: "Hal Finkel" <hfinkel@anl.gov>
Cc: "Ayal Zaks" <ayal.zaks@intel.com>, "Michael Kuperstein" <mkuper@google.com>, "Adam Nemet (anemet@apple.com)"
<anemet@apple.com>, "Sanjay Patel (spatel@rotateright.com)" <spatel@rotateright.com>, "Nadav Rotem"
<nadav.rotem@me.com>, "llvm-dev" <llvm-dev@lists.llvm.org>
Sent: Sunday, September 25, 2016 1:28:58 PM
Subject: RE: RFC: New intrinsics masked.expandload and masked.compressstore

  >
  >Hi Elena,
  >
  >Technically speaking, this seems straightforward.
  >
  >I wonder, however, how target-independent this is in a practical
  >sense; will there be an efficient lowering when targeting any
  >other
  >ISA? I don't want to get into the territory where, because the
  >vectorizer is supposed to be architecture independent, we need to
  >add target-independent intrinsics for all potentially-side-effect-
  >carrying idioms (or just complicated idioms) we want the
  >vectorizer to
  >support on any target. Is there a way we can design the vectorizer
  >so
  >that the targets can plug in their own idiom recognition for these
  >kinds of things, and then, via that interface, let the vectorizer
  >produce
  >the relevant target-dependent intrinsics?

Entering target specific plug-in in vectorizer may be a good idea. We
need target specific pattern recognition and target specific
implementation of “vectorizeMemoryInstruction”. (It may be more
functionality in the future)
TTI->checkAdditionalVectorizationOppotunities() - detects target
specific patterns;

How would this work in this case? The result would need to affect the legality and cost of the memory instruction. From your poster, it looks like we're talking about loops with constructs like this:

for (i =0; i < N; i++) {
if (topVal > b[i]) {
   *dst = a[i];
   dst++;
}
}

is this loop vectorizable at all without these constructs? It looks like the target would need to analyze the PHI representing the store's address, assign the store some reasonable cost, and also provide some alternative SCEVs (perhaps lower and upper bounds) for use with the dependence checks?

X86 will find compress/expand and may be others

What others might fit in here?

TTI->vectorizeMemoryInstruction() - handle only exotic
target-specific cases

Pros:
It will allow us to implement all X86 specific solutions.
The expandload and compresssrore intrinsics may be x86 specific,
polymorphic:
llvm.x86.masked.expandload()
llvm.x86.masked.compressstore()

Cons:

TTI will need to deal with Loop Info, SCEVs and other loop analysis
info that it does not have today. (I do not like this way)

Giving TTI the loop and other analyses, in itself, does not bother me. getUnrollingPreferences takes a Loop*. I'm more concerned about how cleanly we could integrate everything.

Or we'll need to introduce TLV - Target Loop Vectorizer - a new class
that handles all target specific cases. This solution seems more
reasonable, but too heavy just for compress/expand.

I don't see how this would work without duplicating a lot of the logic in the vectorizer (unless it is really just doing loop-idiom recognition, in which case none of this is really relevant). You'd want the cost-model using by the vectorizer, in general, to be integrated with whatever the target was providing.

Thanks again,
Hal

7

From: "Michael Kuperstein" <mkuper@google.com>
To: "Elena Demikhovsky" <elena.demikhovsky@intel.com>
Cc: "Hal Finkel" <hfinkel@anl.gov>, "Ayal Zaks"
<ayal.zaks@intel.com>, "Adam Nemet (anemet@apple.com)"
<anemet@apple.com>, "Sanjay Patel (spatel@rotateright.com)"
<spatel@rotateright.com>, "Nadav Rotem" <nadav.rotem@me.com>,
"llvm-dev" <llvm-dev@lists.llvm.org>
Sent: Monday, September 26, 2016 2:31:41 AM
Subject: Re: RFC: New intrinsics masked.expandload and
masked.compressstore

In theory, we could offload several things to such a target plug-in,
I'm just not entirely sure we want to.

Two examples I can think of:

1) This could be a better interface for masked load/stores and
gathers.

2) Horizontal reductions. I tried writing
yet-another-horizontals-as-first-class-citizens proposal a couple of
months ago, and the main problem from the previous discussions about
this was that there's no good common representation. E.g. should a
horizontal add return a vector or a scalar, should it return the
base type of the vector (assumes saturation) or a wider integer
type, etc. With a plugin, we could have the vectorizer emit the
right target intrinsic, instead of the crazy backend
pattern-matching we have now.

I don't think we want to offload either of these things to the targets to produce target-specific intrinsics - both are fairly generic. There's value in using IR and then pattern-matching the result later because it also means that we pick up cases where the same pattern comes from people using C-level vector intrinsics, other portable frontends, etc. We don't want every frontend wishing to emit a horizontal reduction to need to use target-specific intrinsics for different targets. Our vectorizer should not be special in this regard.

However, this does bring up another issue with our current cost model: it current estimates costs one instruction at a time, and so can't take advantage of lower costs associated with target instructions that have complicated behaviors (FMAs, saturating arithmetic, byte-swapping loads, etc.). This is a separate problem, in a sense, but perhaps there's a common solution.

-Hal

8

------------------------------

*From: *"Michael Kuperstein" <mkuper@google.com>
*To: *"Elena Demikhovsky" <elena.demikhovsky@intel.com>
*Cc: *"Hal Finkel" <hfinkel@anl.gov>, "Ayal Zaks" <ayal.zaks@intel.com>,
"Adam Nemet (anemet@apple.com)" <anemet@apple.com>, "Sanjay Patel (
spatel@rotateright.com)" <spatel@rotateright.com>, "Nadav Rotem" <
nadav.rotem@me.com>, "llvm-dev" <llvm-dev@lists.llvm.org>
*Sent: *Monday, September 26, 2016 2:31:41 AM
*Subject: *Re: RFC: New intrinsics masked.expandload and
masked.compressstore

In theory, we could offload several things to such a target plug-in, I'm
just not entirely sure we want to.

Two examples I can think of:

1) This could be a better interface for masked load/stores and gathers.

2) Horizontal reductions. I tried writing yet-another-horizontals-as-first-class-citizens
proposal a couple of months ago, and the main problem from the previous
discussions about this was that there's no good common representation. E.g.
should a horizontal add return a vector or a scalar, should it return the
base type of the vector (assumes saturation) or a wider integer type, etc.
With a plugin, we could have the vectorizer emit the right target
intrinsic, instead of the crazy backend pattern-matching we have now.

I don't think we want to offload either of these things to the targets to
produce target-specific intrinsics - both are fairly generic. There's value
in using IR and then pattern-matching the result later because it also
means that we pick up cases where the same pattern comes from people using
C-level vector intrinsics, other portable frontends, etc. We don't want
every frontend wishing to emit a horizontal reduction to need to use
target-specific intrinsics for different targets. Our vectorizer should not
be special in this regard.

Generally speaking, I agree, but there's a line after which DAG-level
pattern matching gets really awful. What we do now for partial reductions
on X86 is kinda crazy, IMO.

Assuming GlobalISel (especially for non-AArch64 targets) is a ways off, I
see two ways to simplify this stuff:
1) Have the vectorizer emit target intrinsics directly.
2) Do IR-level pattern matching and lowering, a la CGP, for complicated
constructs.
Each of those comes with its own set of drawbacks.

However, this does bring up another issue with our current cost model: it
current estimates costs one instruction at a time, and so can't take
advantage of lower costs associated with target instructions that have
complicated behaviors (FMAs, saturating arithmetic, byte-swapping loads,
etc.). This is a separate problem, in a sense, but perhaps there's a common
solution.

It's not really a separate problem - as long as the vectorizer and the
lowering don't query a shared source of truth for idiom recognition, I'm
not sure there's a way to assign costs to these idioms with decent
precision. And even if we can get them to make the same query (sounds
practically impossible if lowering happens in DAG, doable but untrivial if
it happens in IR, since for the vectorizer we need to match the
pre-vectorization IR and for lowering the post-vectorization version), I'm
not sure how much of a win it'll be. The more complex the construct, the
higher the chances of it being "blown away" by an intervening
transformation between vectorization and the final pattern matching.

To be clear - I'm not advocating actually moving to a
vectorizer-emits-target-intrinsics model. It doesn't strike me as a very
good solution. I just don't have any better ideas at the moment.

-Hal

9

  >How would this work in this case? The result would need to affect the
  >legality and cost of the memory instruction. From your poster, it looks
  >like we're talking about loops with constructs like this:
  >
  >for (i =0; i < N; i++) {
  > if (topVal > b[i]) {
  > *dst = a[i];
  > dst++;
  > }
  >}
  >
  >is this loop vectorizable at all without these constructs?

Good question. Today it isn't. Theoretically yes if we'll know that only a small part of the loop has cross-iteration dependency or another issue. A loop may be vectorized and contain scalar pieces inside.
But it requires full reconstruction of the cost model.

  > It looks like
  >the target would need to analyze the PHI representing the store's
  >address, assign the store some reasonable cost, and also provide
  >some alternative SCEVs (perhaps lower and upper bounds) for use
  >with the dependence checks?

First of all, this loop should pass legality check. Legality will need an additional effort in order to detect compress/expand pattern in a loop with cross-iteration dependency.
Once the pattern is detected, we mark the "store" as "compressing store" and TTI will give a cost for compressing store.
  >
  >> X86 will find compress/expand and may be others
  >
  >What others might fit in here?
The compress/expand are special patterns that will require a separate analysis. I thought about other X86 specific patterns that may be detected. Strided memory access with masks or arithmetic with saturation. But again, I'm not sure that constructing plug-in will not be an overkill in this case.

10

From: "Elena Demikhovsky" <elena.demikhovsky@intel.com>
To: "Hal Finkel" <hfinkel@anl.gov>
Cc: "Ayal Zaks" <ayal.zaks@intel.com>, "Michael Kuperstein" <mkuper@google.com>, "Adam Nemet (anemet@apple.com)"
<anemet@apple.com>, "Sanjay Patel (spatel@rotateright.com)" <spatel@rotateright.com>, "Nadav Rotem"
<nadav.rotem@me.com>, "llvm-dev" <llvm-dev@lists.llvm.org>
Sent: Monday, September 26, 2016 3:55:27 PM
Subject: RE: RFC: New intrinsics masked.expandload and masked.compressstore

  >
  >How would this work in this case? The result would need to affect
  >the
  >legality and cost of the memory instruction. From your poster, it
  >looks
  >like we're talking about loops with constructs like this:
  >
  >for (i =0; i < N; i++) {
  > if (topVal > b[i]) {
  > *dst = a[i];
  > dst++;
  > }
  >}
  >
  >is this loop vectorizable at all without these constructs?

Good question. Today it isn't. Theoretically yes if we'll know that
only a small part of the loop has cross-iteration dependency or
another issue. A loop may be vectorized and contain scalar pieces
inside.
But it requires full reconstruction of the cost model.

  > It looks like
  >the target would need to analyze the PHI representing the store's
  >address, assign the store some reasonable cost, and also provide
  >some alternative SCEVs (perhaps lower and upper bounds) for use
  >with the dependence checks?

First of all, this loop should pass legality check. Legality will
need an additional effort in order to detect compress/expand pattern
in a loop with cross-iteration dependency.
Once the pattern is detected, we mark the "store" as "compressing
store" and TTI will give a cost for compressing store.
  >
  >> X86 will find compress/expand and may be others
  >
  >What others might fit in here?
The compress/expand are special patterns that will require a separate
analysis. I thought about other X86 specific patterns that may be
detected. Strided memory access with masks or arithmetic with
saturation. But again, I'm not sure that constructing plug-in will
not be an overkill in this case.

I'm fairly certainly that creating a plugin interface just for this would be overkill. Nevertheless, I found this discussion quite helpful. If we can't think of any other examples, I'm fine with this intrinsic as proposed.

Thanks again,
Hal

11

Thank you. I have a BOF slot on LLVM dev meeting where I'll open discussion about intrinsics as a form of vectorizer output.

- Elena