I am going to be starting work on implementing LLDB support for AArch64/Arm64 scalable vector extension (SVE) in coming weeks. For a quick walk through of SVE please read through this doc here: https://www.kernel.org/doc/Documentation/arm64/sve.txt
In summary it allows hardware + kernel which support SVE to have variable vector register lengths which can be configured as per system requirements on per process or thread basis.
I have been informed that there might be some downstream patches and I would like to collaborate with anyone who is willing to contribute their completed or in-progress work.
I would also like to open a discussion on how we can implement variable length registers in LLDB and what could be the consequences of those changes.
Looking forward to hearing from the community.
I am not saying I am particularly happy with how it was implemented, but you should take a look at the "dynamic_size_dwarf_expr" members of the RegisterInfo struct <https://github.com/llvm-mirror/lldb/blob/master/include/lldb/lldb-private-types.h#L57>. These were added to support some variable length registers on mips, and it sounds like they could be useful here too.
Sounds like each register can very in size each time you stop if I read the docs correctly. As Pavel said “dynamic_size_dwarf_expr” might work for you here. Registers in a lldb_private::RegisterContext can have their sizes using:
uint32_t RegisterContext::UpdateDynamicRegisterSize(const lldb_private::ArchSpec &arch, RegisterInfo *reg_info);
Now this function isn’t currently virtual, so it currently has one way to update the register size that must use the RegisterInfo::dynamic_size_dwarf_expr_bytes and RegisterInfo::dynamic_size_dwarf_len members. But it could be made virtual if your the register size couldn’t be determined a DWARF expression and then your register context would need to figure things out on the fly.
lldb_private::RegisterContext has ReadAllRegisterValues and WriteAllRegisterValues that is used to save/restore register state before we modify registers values for an expression that gets run in a thread. This might be tricky for this case if the expression you run modifies the SVE register state and prior to running the expression you have a few registers that are a certain number of bytes in size, but after the expression, they have changed. In that case, can you modify the kernels notion of this so that saving and restoring registers works correctly?