Tablegen PAT limitation?

Hello,

def GPR : RegisterClass<“ABC”, [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;

def MGPR : RegisterClass<“ABC”, [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;

def SGPR32 : RegisterClass<“ABC”, [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15
)>;

def uimm2 : Operand, ImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = “decodeUImmOperand<2>”;
}

possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).

vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!

def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
string Namespace = “ABC”;
dag OutOperandList = (outs GPR:$rs1);
dag InOperandList = (ins SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift);
string AsmString = “LOAD [$rbase + ( $roffset << $rshift )], $rs1”;
list Pattern = [(set v1i16:$rs1, (load (add (v1i32 (bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32 (build_vector uimm2:$rshift))))))];
list Uses = [];
list Defs = [];
list Predicates = [];

-gen-dag-isel -debug

PATTERN: (ld:{ *:[v1i16] } (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedload>><<P:Predicate_load>>
RESULT: (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32] }:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STORErr v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i32:{ *:[v1i32] }:$roffset)

Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!

Any idea to solve this problem?

Hi,

The problem is with a pattern that has a vt in it: the “vtInt …” printed below the error message. Could you run llvm-tblgen from a debugger and show the stack trace from where the error occurred?