[AArch64][intrinsics] llvm.masked.load.nxv16i8.p0nxv16i8

hi, All:
I’m curious about what will the second parameter of llvm.masked.load.nxv16i8.p0nxv16i8 do ?
I try to adjust the value 2 to 4, but the output assemble doesn’t change.

a case related the llvm.masked.load.nxv16i8.p0nxv16i8 can be found in file llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll:

define <vscale x 16 x i64> @masked_ld1b_i8_sext(<vscale x 16 x i8> *%base, <vscale x 16 x i1> %mask) {
   %wide.masked.load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %base, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> undef)
   %res = sext <vscale x 16 x i8> %wide.masked.load to <vscale x 16 x i64>
  ret <vscale x 16 x i64> %res

Alignment: LLVM Language Reference Manual — LLVM 16.0.0git documentation

1 Like

Thanks very much